Views: 0 Author: Site Editor Publish Time: 2026-09-16 Origin: Site
For decades, chip performance gains were almost synonymous with "making transistors smaller." But as processes push to 3nm and below, EUV lithography costs have skyrocketed, and the marginal returns of geometric scaling are visibly diminishing. The entire industry is looking for a new answer.
Technical Path: From Planar to 3D.
Huawei's recent "Tao (τ) Law" offers a perspective worth watching: replacing geometric scaling with time scaling, centered on systematically reducing signal propagation time constants through "logic folding" — distributing circuits across vertically stacked multi-layer active chips. Simply put, it shortens the "commute distance" of electrons inside the chip.
Engineering this law relies heavily on two foundational capabilities: full-stack EDA toolchain collaboration and advanced packaging process maturity. Most existing EDA toolchains optimize area, timing, and power independently for planar chips, while 3D folded designs require treating multi-layer stacked dies as a single design entity.
Practical Supply Chain Implications.
If you're focused on the packaging segment, several technology directions deserve attention:
Hybrid Bonding: The key to high-density interconnect, with surface roughness and alignment precision requirements jumping from micron to nanometer scale.
Panel-Level Packaging: As interposer sizes grow, wafer-level packaging area utilization deteriorates sharply, and panel-level processes are becoming an effective path for high-performance heterogeneous integration.
Co-Packaged Optics (CPO): When interconnect bandwidth becomes the system bottleneck, placing optical engines adjacent to switch chips is pushing "optics in, copper out" to the chip level.
