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The AMD EPYC 9375F is a 32-core, 64-thread server processor belonging to the 5th Gen EPYC 9005 Series, built on the Zen 5 core architecture and codenamed Turin. With an official OPN of 100-000001197, this processor is engineered for data center workloads that require a balance between high per-core frequency and multi-thread throughput. It operates at a 3.8 GHz base clock, reaches 4.4 GHz on all-core boost, and delivers up to 4.8 GHz maximum boost frequency, backed by 256 MB of shared L3 cache. The processor uses the SP5 socket and supports both single-socket and dual-socket server configurations, making it suitable for mid-size database nodes, VDI hosts, and HPC compute clusters. For commercial procurement teams evaluating x86 server CPUs, the 9375F occupies a specific position in the 9005 Series stack: fewer cores than the 64-core 9575F, but with higher base and boost frequencies for latency-sensitive applications.
Model | AMD EPYC 9375F |
|---|---|
Official Tray PN | 100-000001197 |
Architecture | AMD Turin (5th Gen EPYC 9005 Series) |
Core / Thread | 32 Core / 64 Thread |
Base Frequency | 3.8 GHz |
All-Core Boost | 4.4 GHz |
Max Boost Frequency | Up to 4.8 GHz |
L3 Cache | 256 MB |
CPU Socket | SP5 |
Supported Configuration | 1-Socket / 2-Socket |
Memory Support | 12 Channel DDR5 RDIMM/MRDIMM |
Max Memory Speed | DDR5 6400 MT/s (1DPC) |
Single Socket Memory Bandwidth | 614 GB/s |
PCIe Interface | PCIe 5.0, total 128 Lanes |
Default TDP | 320 W |
Configurable cTDP | 320 W - 400 W |
Security Tech | AMD Infinity Guard Secure Encryption |
Launch Date | Oct 10, 2024 |
The 9375F pairs 32 Zen 5 cores with a 256 MB L3 cache, providing a large last-level cache footprint for in-memory datasets and frequently accessed instruction pages. The 3.8 GHz base clock ensures sustained frequency under full-load conditions, while the 4.4 GHz all-core boost and 4.8 GHz max boost address applications where single-thread latency directly impacts transaction throughput, such as online transaction processing (OLTP) databases and virtual desktop infrastructure (VDI) session hosts.
Each socket supports 12 channels of DDR5 memory at up to 6400 MT/s in 1DPC configuration, yielding a theoretical memory bandwidth of 614 GB/s per socket. This bandwidth level supports memory-intensive workloads including in-memory databases, large-scale virtualization density, and HPC simulation codes. The processor also provides 128 lanes of PCIe 5.0 connectivity, enabling direct attachment of high-speed NVMe SSDs, 200 GbE network adapters, and GPU accelerators without requiring PCIe switch chips in many server designs.
The 9375F has a default TDP of 320 W and supports a configurable cTDP range of 320 W to 400 W. Data center operators can adjust the power envelope based on available cooling infrastructure and workload requirements. Lower cTDP settings reduce power consumption and thermal output for energy-constrained deployments, while higher settings allow the processor to maintain elevated frequencies for compute-bound tasks. This flexibility helps enterprise customers align processor power profiles with rack-level power budgets and cooling capacities.
The processor integrates AMD Infinity Guard, a set of hardware-level security features including secure memory encryption (SME) and secure nested paging (SEV-SNP). These features enable confidential computing deployments, virtual machine isolation, and protection against physical memory attacks. For financial services, government, and healthcare workloads handling regulated data, these hardware-backed security capabilities are evaluated during the procurement and compliance review process.
The combination of 32 cores, high boost frequencies, and 12-channel memory makes the 9375F suitable for VDI deployments where per-session responsiveness depends on single-thread performance. In hyper-converged infrastructure (HCI) nodes, the PCIe 5.0 ×128 lane count supports direct-attached NVMe storage and high-bandwidth networking without lane contention.
For MySQL, PostgreSQL, and Redis clusters, the 256 MB L3 cache and high memory bandwidth reduce disk I/O pressure by keeping larger working sets in cache. Dual-socket configurations scale memory and core count for distributed analytical workloads.
The processor supports CAE, CFD, and electronic design automation (EDA) workloads that benefit from high per-core performance. When paired with PCIe 5.0 GPUs, it can serve as a host CPU for lightweight AI inference and vision recognition workloads.
The AMD EPYC 9375F uses the SP5 socket, which is the standard socket for the 5th Gen EPYC 9005 Series. It is not pin-compatible with the earlier SP3 socket used by 1st, 2nd, and 3rd Gen EPYC processors.
The processor supports 12 channels of DDR5 RDIMM or MRDIMM at up to 6400 MT/s in 1DPC configuration. Actual maximum capacity per server depends on the motherboard design and DIMM density.
Yes, the 9375F supports both 1-socket and 2-socket configurations. In dual-socket deployments, the two processors communicate via AMD Infinity Fabric interconnect, enabling NUMA-aware applications to scale across both sockets.
The default TDP is 320 W. The configurable cTDP range is 320 W to 400 W, allowing data center operators to tune power and performance based on cooling capacity and workload requirements.